A 25GHz 100ns lock time digital LC PLL with an 8-phase output clock

A digital LC PLL in a 40nm CMOS technology achieves a 100ns lock time and a 16% tuning range while producing an 8-phase output clock with less than 2° phase error up to 25GHz. Fast lock is achieved by calibrating the phase of the feedback clock. The 8-phase output clock is generated using a loop of four digitally-controlled magnetically-coupled LC oscillators. The architecture is suitable for fast-wakeup links.