Low-Power $V_{\bf DD}$/3 Write Scheme With Inversion Coding Circuit for Complementary Memristor Array

The conventional
$V_{\bf DD}$
/3 write scheme is very advantageous in minimizing the unwanted resistance change in unselected cells during the write time. This is due to the fact that an amount of applied voltage at the unselected cells is reduced from
$V_{\bf DD}$
/2 in the
$V_{\bf DD}$
/2 scheme to
$V_{\bf DD}$
/3 in the
$V_{\bf DD}$
/3 scheme. However, the
$V_{\bf DD}$
/3 scheme should sacrifice much larger switching power than the
$V_{\bf DD}$
/2 scheme for having smaller voltage applied at the unselected cells. In this paper, we propose to combine the
$V_{\bf DD}$
/3 scheme with the inversion coding circuit to alleviate large switching power of the
$V_{\bf DD}$
/3 scheme. The proposed
$V_{\bf DD}$
/3 scheme with the inversion coding circuit is verified for 500 × 500 and 1000 × 1000 passive memristor array with the operating frequency of 10 MHz to save power consumption as much as 19% than the conventional
$V_{\bf DD}$
/3 scheme. For 50 MHz, the power saving is more improved to reach as much as 34%. In addition to this power saving, due to the reduced number of bit transitions in the inversion coding, the number of write cycles can be increased by as much as 39% thereby the poor endurance of complementary resistive switch array can be compensated significantly.