Process integration of backside illuminated image sensor with thin wafer handling technology

In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of CMOS image sensor is temporarily bonded to a silicon carrier wafer with thermal plastic material and ZoneBond technology. Then the CMOS wafer is thinned down to few microns to detect the light from the backside. After thinning process, the backside is permanently bonded to a glass carrier substrate with a transparent thermal set bonding material. By using a special trim from glass step, the temporarily bonded silicon carrier could be removed. Cu/Sn micro-bump is then fabricated at the front-side of the CMOS image sensor. No TSVs are needed in the proposed structure. A 300 mm silicon wafer with micro bumps bonded on 500 μm-thick glass wafer is demonstrated. Void free bonding is obtained by IR inspection both in temporary bonding and permanent bonding processes. The thickness of the silicon wafer is measured by IR system and the average thickness of the silicon wafer is 6.4 μm. After thinning, 1 μm TTV is obtained because the thermal plastic material flow during bonding process resulted in excellent planarization. From the cross sectional SEM image, Cu/Sn micro bump with thickness 4 μm/5 μm is formed at the front-side of the CMOS image sensor. The run-out issues from CTE mismatch is also discussed in this study.