Analysis of power integrity and its jitter impact in a 4.3Gbps low-power memory interface

An innovated low-power memory interface with data rate up to 4.3Gbps presents unique challenges to power integrity (PI) design and verification. While benign to power saving, the employed low-power design techniques, such as power state management, low-power clocking circuit, and on-chip voltage regulator, make the interface more susceptible to supply noise, particularly, in terms of its jitter impact. A systematic approach of analyzing power supply noise induced jitter (PSIJ) at design stage is critical to ensure the robustness of such low-power interface. In this paper, the methodology and simulation results are presented in concert with the correlation data. It is shown that when in fully active state, the steady-state on-chip supply noise is 4mV
_pp
and its PSIJ timing impact is 1.7%UI for the 4.3Gbps operation. However, during power state transition the transient supply noise deteriorates to more than 20mV
_pp
and the corresponding PSIJ impact is as high as 11.3%UI.