3D Integration of CMOS image sensor with coprocessor using TSV last and micro-bumps technologies

This paper presents the prototype of a 3D circuit in which a Wafer Level Packaged CMOS image sensor is vertically assembled with an image signal processor in a face-to-back integration scheme. The design flow used to hybrydize the two circuits will be fully described, up to physical implementation. The process technology carried out will be presented in a 200 mm environment. Finally, the 3D assembly will be successfully assessed, concretising the realism of a 3D technology for nomadic imaging systems.