Total cost effective scallop free Si etching for 2.5D & 3D TSV fabrication technologies in 300mm wafer

In recent years, "2.5D silicon interposers" and "Full 3D stacked" technology for high-performance LSI has attracted much attention since this technology can solve interconnection problems using TSV (Through Silicon Via) to electrically connect stacked LSI. 2.5D and 3D Si integration has great advantages over conventional 2D devices such as high packaging density, small wire length, high-speed operation, low power consumption, and high feasibility for parallel processing. But, the radical problem about the TSV production cost is not still solved. In particular, the demand to a new plating bath technology to shorten Cu plating time is expected. On the other hand, TSV isolation liner materials with lower cost for high frequency devices will be necessary in future. “Scallop-free” etching process has developed for TSV fabrication [1]. And, the smooth-sidewall had proved shorten PVD process time [2]. At first, it investigated a cost correlation of taper-shape etching and Cu-ECP (electrochemical plating) in this paper. And then, a polyurea film using a vapor deposition polymerization technology (which is Ulvac's FPF/PV large panel technology) tried introduction as isolation liner for next-generation high frequency device. And, it performed the film formation to a TSV pattern.