Accelerated reliability testing and modeling of Cu-plated through encapsulant vias (TEVs) for 3D-integration

Through encapsulant vias (TEVs) are an interconnect technology which enables 3D stacking and double sided re-routing of packages encapsulated with epoxy molding compound. These interconnects are formed by Cu-plated holes through the encapsulant and can typically be routed by an RDL (redistribution layer). In order to enable prolonged function of these interconnects, thermo-mechanical reliability has to be assured. Dedicated stress tests have to be conducted to evaluate lifetime under relevant testing conditions, then failure mechanisms have to be identified, understood and quantitatively condensed into a lifetime model to predict reliability for future designs. In order to assure a short time to market, accelerated tests (and corresponding acceleration factors) are urgently needed by industry and are the holy grail of reliability as an academic discipline. The idea presented in this paper is to substitute lengthy thermal cycling tests by results obtained by rapid isothermal fatigue tests at different temperatures and establish a correlation between both of them. Based on physics of failure principles, the applicability and viability of such a concept then is evaluated and discussed. In conclusion, this work shows a consistent approach for acceleration of the design for reliability procedure in system integration. It is based on the now possible rapid generation of a lifetime model by thin metal layer samples which are easily manufacturable with the same technology as the TEVs. More data is needed to confirm the failure mechanisms in TEVs, reproducible samples for thermal cycling and to validate the applicability of the method also to other metal layers used in the electronic packaging industry.