Simulation to Study the Effect of Oxide Thickness and High-$K$ Dielectric on Drain-Induced Barrier Lowering in N-type MOSFET

The effect of variation of oxide thickness on the drain-induced barrier lowering, simulation parameter of a conventional MOSFET has been studied, first theoretically by proposing a new numerical method and then verifying by simulating with Sentaurus TCAD Toolkit. Since SiO
₂
has its limitations at very low oxide thicknesses, improvement in the performance of the MOS by using high- K dielectric material for gate-channel isolation has also been studied.