A 0.9 V low-power reconfigurable successive approximation ADC for integrated sensors

In this paper, a reconfigurable successive approximation analog-to-digital converter with selectable resolutions ranging from 7 to 10 bits is presented. The circuit is implemented in IBM CMOS 0.13 μm technology, and operates with a 0.9 V supply. The simulated effective number of bits (ENOB) ranges from 6.66 to 9.75, while the simulated power consumption during a continuous conversion ranges from 194 nW (7 bits) to 418 nW (10 bits) at a sampling rate of 50 kS/s.