Design of an embedded RF signal generator for BIST application

This paper presents the design of an RF test signal generator for a Built-In-Self-Test (BIST) application. This embedded generator is the most sensitive part of a new BIST architecture which basically, consists of integrating an RF generator at the RF Front End input and an RMS detector at the IF side on chip at lowest cost. The proposed BIST cell targets a direct low cost measurement of the gain and the input 1dB compression point (CP1) of a K-band satellite reception chain (18.2 GHz − 22 GHz). The BIST generator, designed in a BiCMOS process, consumes 10 mA. Its power range is equal to 17 dB [−45 dBm; −28 dBm] and its frequency varies from 17.5 GHz to 23.1 GHz. This BIST circuit provides new perspectives in terms of production test strategy, cost reduction and measurement accuracy for mm-wave integrated circuits.