Study of threshold voltage of p-channel four gate transistor

A three dimensional model of SOI p-channel four gate transistor has been developed using device simulator Silvaco/ATLAS. Threshold voltage for the device is studied for different biasing condition at the four gates and different physical parameter like channel length. The results are compared to the results obtained from the analytical model of threshold voltage of n-channel four gate transistor to find out whether the analytical model works for p-channel G
⁴
-FET also.