A digitally-calibrated 10GS/s reconfigurable flash ADC in 65-nm CMOS

The design of a high-speed reconfigurable analog-to-digital converter in 65-nm CMOS is described. Accuracy requirements are met without compromising the high-speed performance by using trimming-based offset cancellation. The ADC can be configured to work as a 3-bit, a 4-bit, or a 5-bit ADC with maximum integral nonlinearity (INL) and differential nonlinearity (DNL) of 0.48LSB and 0.35LSB respectively. The ADC achieves a figure-of-merit of 0.46pJ/conv-step and the active area is 0.13 mm
²
.