SSC tracking analysis and a deeper-SSC estimator

This paper examines two kinds of bang-bang semidigital dual loop CDR architectures: 2^nd-order and 3^rd-order. Quantitative analysis is made in detail between the two in the presence of spread spectrum clocking (SSC) which hasn't been well studied. Moreover, a novel SSC estimator based on 3^rd-order architecture is proposed to suppress the frequency-overshoot of conventional 3^rd-order CDR happening at the switching points of SSC. The depth of its SSC tracking may be up to 10000ppm at 30 KHz which helps to reduce EMI.