ATM traffic shaper: ATS

The design and Implementation of an ATM Traffic Shaper (ATS) is described. This IC was realised on a 0.35 /spl mu/m CMOS technology. The main function of the ATS is the collection of low bit rate traffic to fill a higher bit rate pipe in order to reduce the cost of ATM based services, nowadays mainly influenced by transmission cost. The circuit fits in several ATM system configurations but mainly will be used at the User-Network Interfaces or Network-Network interfaces. The IC was designed with a top-down methodology using as HDL, Verilog. The chip is pad limited and is encapsulated in a 208 PQFP package. The circuit complexity is 38 Kgates and its working frequency is 32 MHz. A circuit prototype was build with FPGAs in order to validate the RTL description.