A low offset fast settling rail-to-rail stable operational amplifier in 180 nm technology

This work presents the design of a modified two stage operational amplifier in 0.18 μm CMOS technology. The main objective of the design is to make a trade-off between offset voltage and power consumption while maintaining rail-to-rail output swing and high phase margin. For this purpose, transistors with controlled region of operation are included to the output stage. Simulation is done in Cadence Spectre with 1.8V power supply. Simulation results show that the designed OPAMP consumes 616.31 μW power with high phase margin of 70.6° and very low offset voltage of 16.91 μV, maintaining rail-to-rail output swing.