Integrating spin-torque-transfer magnetic memory in a 65 nm low power CMOS technology

This paper shows results of the integration of a 65 nm low power CMOS technology with spin-torque-transfer magnetic memory. This effort has focused upon a set of compatible, stable, and high yielding fabrication modules. Magnetic Tunnel Junction (MTJ) devices from a 64Mb array are shown and the device radiation hardness is demonstrated.