Fast analog front-end for the readout of the SuperB SVT inner Layers

The SuperB factory is an Italian e+ e- accelerator project that plans to reach a luminosity higher than 10
³⁶
cm
^-2
s
^-1
by means of a very small beam size and with moderate beam currents. To achieve the performance imposed by physics, six layers of microstrip silicon sensors, with different pitches and lengths, are foreseen in the present design of the Silicon Vertex Tracker (SVT). The SuperB SVT readout chip for inner Layers (L0-L3) is a 128-channel mixed-signal integrated circuit in a 130 nm CMOS technology. Each channel consists of a charge-sensitive preamplifier, a second order unipolar semi-Gaussian shaper, a baseline restorer and a hit discriminator. A 4 bit A/D conversion will be performed by means of the Time-Over-Threshold (ToT) technique. This paper presents the solutions adopted in this chip for the analog channel building blocks and discusses the simulation results for the current design along with the expected performance in terms of parameters such as signal-to-noise ratio, dynamic range, linearity, power dissipation and hit time resolution.