Time amplification using closed-loop differential amplifier

This paper describes a new time amplifier (TA) architecture based on differential difference amplifier (DDA) in unity gain buffer configuration. The proposed TA is aim to improve the gain, input range, and capability to control the timing gain. Simulation results indicated that the peak deviation between ideal and actual TA transfer curve has been reduced to about 7ps, and the maximum input range and gain are 60ps and 20, respectively. The TA is also applied to a 9-bit two-stage vernier delay line (VDL) TDC. The TDC has sampling rate of about 8Msps, and the time resolution of 3ps with differential non-linearity (DNL) within -0.5 and 0.9 LSB, and integral non-linearity (INL) within -0.8 and 1 LSB. Both the TA and TDC are implemented using TSMC CMOS 0.18um 1P6M technology.