Multi-channel charge pulse amplification, digitization and processing ASIC for detector applications

For the charge readout of the TRD sub-detector of the upcoming fixed-target experiment CBM at FAIR/GSI, a dedicated 32-channel mixed-signal readout ASIC is being developed in 180 nm. The first full-blown version called SPADIC 1.0 was submitted end of 2011 and is currently being tested in the laboratory. The SPADIC ASIC is a complete readout system from analog input charge to digital output protocol and hereby provides an oscilloscope-like readout scheme. Each channel consists of an amplifier (CSA, 800eENC), a continuously running pipeline ADC (8 bit effective, 25 MSamples/s), a digital filter (4-stage IIR), a hit detection logic (self-triggered), a message building mechanism, and finally an output buffer. The messages in the output buffers are arbitrated to one message stream, which subsequently is transmitted via a complex protocol serially over two 500 Mbitfs LVDS links out of the chip. The list of additional features is long, making the SPADIC ASIC a flexible solution for various detector applications.