Design of stochastic Viterbi decoders for convolutional codes

The Viterbi algorithm is widely used to decode convolutional codes. We present an unconventional approach to Viterbi decoder design based on stochastic computing (SC) which represents data by random bit-streams that can be interpreted as probabilities. Stochastic circuits allow many decoding functions to be implemented by simple hardware; e.g., multi-bit multiplication can be realized by an AND gate. SC is also highly error-tolerant since a soft error (bit-flip) has little impact on a SC number's value. It also allows decoding precision to be traded for decoding speed. We design two SC-based Viterbi decoders and also a hybrid binary-SC design; the latter uses SC for arithmetic calculations, but not for storing numbers. The proposed designs are compared with a binary (non-SC) decoder using a standard (7, 1/2) convolutional code. The SC designs are found to be more tolerant of soft errors in the decoder than the binary design, and more capable of supporting some useful trade-offs among area cost, data rate, precision, and bit-error rate.