Enabling thermal IL and ALD HfOx integration for sub-20nm gate stack

World class EOT scaling and reliability performance has been achieved by integration (no air-break) of thermal interface layer (IL) and ALD high-k. RTP process is used for the formation of Ultra-Thin IL (UT-IL) and Mono-Layer IL (ML-IL). While integrated with ALD HfO
_x
process, the resultant dielectric stack can reach 6Å EOT with excellent gate leakage, mobility and BTI reliability performances. The experiment also demonstrates that integrated thermal IL/HfO
_x
stack provides lower pre-existing trap density and lower trap generation during BTI when compared to conventional chemical oxide IL/air-beak/HfO
_x
stack.