Thermal mismatch induced reliability issues for Cu filled through-silicon vias

This paper reports on experiments assessing 3 potential impacts and reliability risks induced by the thermal mismatch between Cu and Si in Cu filled through-silicon via (TSV) integration in 3D technology. The results show that (1) the Cu stress is a higher contributor to stress in the Si than FEOL film edge effects induced by TSV etch; (2) Cu extrusion induced by BEOL processing does not lead to severe delamination/cracking in low-k BEOL layers above the TSV; (3) stress induced at the TSV bottom does not cause visible damage to the liner or backside passivation after wafer thinning.