A junction leakage mechanism and its effects on advance SRAM failure

Junction leakage is becoming an important reliability concern as shallow trench isolation (STI) continues to scale down. This junction leakage has to be considered to improve SRAM Vccmin degradation. The major index of junction leakage in SRAM cell is found to be off-state leakage current as the leakage phenomenon externally manifests as a current flow from butted contact (BCT) to lower pull down (LPD) transistor gate. Isolation test patterns (P
⁺
/N-well to P-Well) with well photo misalignments are designed to verify Si/STI interface damage effect on junction leakage. Process experiment with PW misalignment shows isolation leakage current (P
⁺
to PW) increase after electrical stress. However, this type of leakage due to PW misalignment shows weak temperature and voltage dependence, indicating that the trap-assisted carrier hopping at STI Si/SiO
₂
interface and the PW misalignment are paramount of SRAM junction reliability. Using TCAD simulation, we have verified that carriers transport through the Si/STI interface traps along with poor PW misalignment is the root causes of the junction leakage current increase. HSPICE simulation results show that junction leakage worsen SRAM cell stability by degrading SRAM read margin (SNM) and may eventually lead to cell failure.