Reed-solomon decoder hardware implementation for DVB-S receiver

In this paper, a shortened Reed-Solomon decoder (n=204, k=188) is simulated using MATLAB and Maple programs within Digital Video Broadcasting - Satellite standards. Then, it is modelled and its hardware is implemented regarding to speedy, flexible, and straightforward production on FPGA using VHDL. Due to speed, flexibleness, and easy fabrication, the cellular-array multiplication method is used for the commonly used arithmetic operation, finite field multiplication. Reformulated inverse-free Berlekamp-Messey Algorithm, capable of high speed and low complexity, is implemented succesfully for key equation solver unit.