Investigation of the failure mode formation in BGA components subjected to JEDEC drop test

This paper is an investigation of the root causes for changing failure modes in different package types which are subjected to constant JEDEC drop test conditions. Drop test experiments applying memory BGA components show that there is more than one ultimate failure mode and that the failures created in the 2
^nd
level interconnections are dependent on the package type. Thus the package geometry causes a redistribution of stress in the solder balls resulting in a stress concentration at the observed failure position. Stress analyses of the investigated packages are done by explicit finite element simulations in order to identify the significant stress distribution changes within the solder interconnections. These analyses prove different stress distributions resulting in the observed experimental failure modes. Additionally, these stress distributions justify the unexpected appearance of higher characteristic lifetimes for bigger packages.