Measurements of SRAM sensitivity against AC power noise with effects of device variation

SRAM exhibits the sensitivity of false operation against static and sinusoidal supply voltage variation. A measurement system combines direct radio frequency (RF) power injection, on-chip monitoring of voltage variation on power supply lines, and built-in self test of memory read/write operations. The bit error rate (BER) of an SRAM core exponentially increases when the lowest instantaneous voltage on the power supply line of SRAM cells during RF injection linearly decreases. Test dice on wafers at five different process corners in a 1.5 V 90 nm CMOS technology were tested. The minimum allowable voltage with BER of less than a single bit failure in average becomes smaller, thus more tolerant, when n-channel devices are at the slow corner in a conventional 6-transistor SRAM cell. The measurement technique enables to experimentally evaluate dynamic noise margin of SRAM cores in a given technology.