Design and Verification of nMOSFET for Low Leakage at 90nm Process Technology

The development of MOSFET technology in the VLSI era has been governed by the device scaling. When a MOSFET is scaled into the deep sub-micrometer region several types of leakage components are come in to the picture. Low power MOSFET devices can be developed from advanced fabrication process. Once the channel length and oxide thickness of MOSFET are selected, the most important process changes are implant conditions like surface implant, halo and source drain extension implant. In this paper low leakage and high performance 90nm channel length MOSFET is optimized. The parameters under investigation are VT, ID-VG characteristics and ION/IOFF relation.