Porous Si as a substrate material for RF passive integration

Thick porous Si layers locally formed on a low resistivity Si wafer were studied for their application in on-chip RF device integration. A comparison was made between the above porous Si substrate and trap-rich high resistivity Si (trap-rich HR Si), which constitutes a state-of-the-art substrate for RF integration, by integrating identical co-planar waveguide transmission liness (CPW TLines) on both porous Si layer/low resistivity Si and trap-rich high resistivity Si. It was showed that signal attenuation on the porous Si layer is 30% lower than on trap-rich HR Si. This suggests lower losses or better RF shielding in the case of porous Si. In addition, CPW TLines were designed and realized on porous Si substrate for the frequency range 1–110GHz. The measured attenuation constant at 60 and 110GHz was respectively 0.33 and 0.55 dB/mm. This result competes very well with the best literature results on CMOS integrated transmission lines, even though the metal lines in the case of the porous Si substrate were not optimized.