Thermal stress and die-warpage analyses of 3D die stacks on organic substrates

Packaging of 3D die stacks on organic laminates is a low-cost approach to achieve devices with high density I/O and short wiring delays. However, the large mismatch in coefficients of thermal expansion between components in the package causes deformation and high stress in the constituting elements. The components such as thin dies, metal through silicon vias, fine-pitch interconnections are susceptible to failures under high stress. In this study, we assessed the potential challenges in packaging of 3D die stacks on organics laminates. The challenges are the die-warpage in assembling and the thermal stress on fine-pitch interconnections in device's reliability. We used test vehicles with 40μm pitch full-area-array interconnections for the study. We observed a significant warpage in the stacked 50μm thick silicon dies at room temperature. We measured the warpage at several temperatures and analyzed using the multilayered beam theory. The simulated values assuming zero warpage at the melting temperature of the SnAgCu solder (220°C), were consistent with the measured values. The analysis showed that the die-warpage occurs due to the mismatch of CTE between silicon dies with Cu-TSVs and the top die without any TSVs. Previous study of the 40μm pitch test vehicle showed that one could widen the selection range of the mechanical properties of the interchip underfill materials by optimizing the silicon interposer thickness. In this study, we extended the analysis to the die stacks with interconnection pitch of 20μm and 80μm and show that one can achieve low-stress packaging by optimization of the silicon die thicknesses.