A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy

A post-process carrier injection scheme for 6T-SRAM is proposed. The proposed scheme pinpoints and simultaneously repairs only cells that have low read disturb margin by injecting electrons to the strong pass gate transistor. Compared with the conventional electron injection scheme that injects electrons to either side of the pass gate transistor of all cells, the proposed scheme achieves 57% less BL delay, 31% less read energy, 32 ~ 256 times shorter injection time and 3% area reduction. The concept is validated with 2, 64, 128 kb SRAM in 40 nm standard CMOS process. Experiments show around 40 mV operation margin increase after the proposed injection.