A 24-Gb/s source-series terminated driver with inductor peaking in 28-nm CMOS

We designed and tested a 24-Gb/s source-series terminated (SST) driver in 28-nm CMOS. The driver is composed of four segments with different weights to achieve an adjustable tap-weight finite-impulse-response (FIR) filter. The driver consists of nine slices, each of which contains four driver units. Each driver unit has a minimum-sized output stage regardless of the tap weight to reduce the power consumption of the preceding pre-driver stages. Series inductors connected to the output terminal of the driver are used to form a π-network circuit to enhance the bandwidth. The driver consumes 27.8 mW off a 0.85-V single supply. The total output jitter is 14.9 ps, which includes an input jitter of 11.1 ps. The core area is 330 × 330 μm2 with bumps.