A 0.2V 16Kb 9T SRAM with bitline leakage equalization and CAM-assisted write performance boosting for improving energy efficiency

An energy efficient 9T SRAM with bitline leakage equalization and Content-Addressable-Memory-assisted (CAM-assisted) performance boosting techniques is presented. The equalized read bitline leakage improves the read bitline swing by 6.8 x at 0.2V. The proposed CAM-assisted boosting technique enhances the write performance of the multi-threshold CMOS (MTCMOS) SRAM array implemented with higher-V
th
(HVT) devices. The inserted tiny CAM conceals the slow data development after data flipping, and therefore improves overall operating frequency in the near threshold region. A 16Kb SRAM test chip was fabricated in 65nm CMOS technology and showed the minimum energy of 0.33 pJ at 0.4V.