High performance and reliable TO package

The development of new TO package towards package miniaturization trend for improving cost performance while enhancing product performance to low ohmic resistance and high current capability had brought challenges into the design for manufacturability and reliability. An innovation of TO package, TO Leadless (TOLL), enables Infineon to maintain technology leadership in Power Semiconductors and competitiveness of business in offering latest product technologies and solutions for Automotive application. The design of TOLL increased the power density and it has large die pad area for power chip size maximization and low profile lead structure for short wire bond looping are greatly contributing to low ohmic resistance and high current capability. The Automotive MOSFET product characterization showed TOLL performed ohmic resistance (Ron) lower and current rating higher than D2PAK. The lead post design of TOLL for power and logic interconnects provides compatibility for broad range of power semiconductors family such as MOSFET, high current PROFET, Power PROFET, Connect FET, NovalithIC, Complimentary MOS, SiC JFET and others. The unique design of TOLL also enables economies of scale in manufacturing and avoids additional cost for conversion at mold tool and test contactor in handling difference products. Throughout development of TOLL, an invention “intrusion mold edge” design was patented and implemented in TOLL for production handling enhancement. As TOLL design is optimized to a low profile leadframe and molded body package for power enhancement, die attach interconnects reliability performance had become a great challenge. The optimization of die attach process did not demonstrate improvement of solder fatigue stress after temperature cycling of reliability test. The die attach solder fatigue due to thermal-mechanical stress, package and chip mechanical designs were characterized to determine the most effective approach to enhance the reliability performance. The innovation is to introduce appropriate chip thickness to minimize the thermal-mechanical stress. As a result, TOLL achieved a high performance and reliable package while maintaining the cost effectiveness.