7-bit 2.56 GS/s folding ADC with nanometric compatible architecture by using a high dynamic I/O folding amplifier

The technological trends to scale down the IC manufacturing processes presents some limitations and problems in the ADC's designs, such as a) poor resolution, b) electronic noise, comparable to quantization steps, c) obsolete topologies, d) second-order physical effects, etc. The nanometric technologies inherently provide greater speed to the ADC's, but not necessarily lower power and area consumption. This paper proposes a 7-Bit 2.56 GS/s folding ADC architecture using a high dynamic I/O folding amplifier designed in 45 nm PD SOI-CMOS technology. Full transistor level simulations for the ADC, working at 2.56 GS/s sampling frequency, are presented. The measured DNL is -0.30/0.24 LSB and the INL is -0.29/0.49 LSB. This architecture achieves 41.133 dB of SNR, 6.54 bits ENOB, 5.2 mW of power consumption, with 1V bias supply, and 2.799 pJ/s of FoM.