Design of an automated test bed for experimental Si and SiC SGTO devices

In a collaborative effort between Army Research Lab (ARL) and Texas Tech University's center for Pulsed Power and Power Electronics (P3E) lab, a high power, high energy test bed meant to characterize experimental Si and SiC Super Gate Turn Off (SGTO) devices was designed and built. The system was engineered to run the devices through an arbitrary number of test cycles while recording all pertinent data automatically. Test parameters are set through a windows GUI which communicates with a microprocessor - based control system that orchestrates timing and settings of each subsystem as well as acquiring voltage and current waveforms with high speed ADCs operating simultaneously in parallel. The test waveform itself is generated by a Pulse Forming Network (PFN) which accurately controls rise time, fall time and pulse width. The PFN is charged by a Rapid Capacitor Charger (RCC) system designed at the P3E lab that is capable of 10 kW and allows precise charge voltage levels to be set. Waveforms are acquired through isolated probes specifically designed to capture desired signals even in the presence of a large bias voltages.