Efficiency improvement in RNG using a simplified algorithm

Computers' required random numbers initially, for simulations and numerical computations like Monte Carlo calculations. Random number generators offer an important contribution to many cryptographic systems. They are critical components in computational science. However the tradeoff between quality and computational performance is an issue for many numerical simulations. FPGA optimized RNGs are efficient in terms of resources than other types of software-based RNGs which means that they can take advantage of bitwise operations and FPGA based specific features. A class of FPGA based RNG called a LUT-SR RNG is illustrated using an algorithm Shift registers are used to improve mixing rate between numbers. Results will be misleading when correlations exist between the random numbers and hence permutations are used. The LUTs are configured into shift registers. The algorithm is simplified based on the architecture such that it ensures longer periods. A generator with a period of 2
^r
− 1 can be implemented and provides r random output bits. This provides a good quality balance compared to previous generators. The critical path between all registers is a single LUT. The program is run in Model Sim 6.4a and implementation is done using Xilinx PlanAhead Virtex5 kit.