Process related challenges for 3D face to face stacking test vehicles using a 40/50μm pitch CuSn microbump configuration

There are several motivations for moving to 3D IC technology. One of the key factors is performance enhancement which can be achieved by further miniaturization of the IC. As more and more functionality is required on a smaller footprint, 3D stacking is a very valuable solution. The increased use of multi-chip integration schemes that use microbumps, Cu pillars and TSVs introduces however severe requirements in term of bump uniformity, height, profile and pitch making 3D stacking exponentially challenging. In this paper we introduce some of the challenges to enable microbumps with pitch of 50μm and below. We also propose process optimizations to enable 3D face to face stacking of a test vehicle. An improvement of the bump plating has been demonstrated by adding a plasma treatment prior to plating. The optimized bumping process has been validated by shear test and electrical characterization of 3D stacks.