A 2.0 V, 0.35 /spl mu/m partially depleted SOI-CMOS technology

A 0.35 /spl mu/m SOI CMOS technology has been demonstrated with excellent partially depleted device characteristics, minimal floating body effects, a unique Schottky body tie scheme, and 1 M SRAM yield approaching bulk CMOS. A state-of-the-art microprocessor fabricated on SOI showed greater than 20% performance improvement over bulk CMOS at the same VDD, or 50% reduction in power dissipation at the same operating frequency.