A novel isolation-scaling technology for NAND EEPROMs with the minimized program disturbance

This paper describes the key technology to realize a scaled NAND EEPROM with the minimized program disturbance. It has been clarified for the first time that the program disturbance caused by neighboring cells is drastically improved by reducing the field implantation dose. The limitation of conventional LOGOS width is estimated to be about 0.56 /spl mu/m. Moreover, a careful device design and an optimization of the bottom implantation are essential in an advanced STI cell.