Integration of (Ba,Sr)TiO/sub 3/ capacitor with platinum electrodes having SiO/sub 2/ spacer

An integrated BST capacitor with Pt electrodes and TiSiN diffusion barrier, covered by SiO/sub 2/ spacers, is fabricated. Excellent diffusion barrier and oxidation resistant properties of TiSiN, further protected from being oxidized by the SiO/sub 2/ spacer, make post annealing up to 650/spl deg/C possible. The 0.3/spl times/0.8 /spl mu/m/sup 2/ sized capacitor having 0.2 /spl mu/m height with 256 M density shows 72 fF/cell of capacitance and 1.0 fA/cell@+1.0 V of leakage current density after the post annealing at 650/spl deg/C. The capacitance corresponds to a value of 25 fF/cell of a DRAM with 0.30 /spl mu/m-pitch, which is expected to be the cell size of 1 giga-bit density DRAM.