A salicide-bridged trench capacitor with a double-sacrificial-Si/sub 3/N/sub 4/-sidewall (DSS) for high-performance logic-embedded DRAMs

We propose a Double-Sacrificial-Si/sub 3/N/sub 4/-Sidewall (DSS) technology to develop a salicide-bridged trench-capacitor cell for high-performance logic-embedded DRAMs. Both the DSS technology and the salicide-bridging are fully compatible with high-performance CMOS processes. With these technologies, a storage node of a Substrate-Plate Trench (SPT) capacitor can be connected to a drain node even over a thick oxide collar during the silicidation.