A monolithic watt-level SOI LDMOS linear power amplifier with through silicon via for 4G cellular applications

In this paper, the design and measurement results of a thin-film SOI LDMOS linear Power Amplifier (PA) integrated in a 0.13μm SOI CMOS industrial process with a Through Silicon Via (TSV) option are reported. First, the power stage of the linear PA has been characterized. At 900MHz under 3.6V supply voltage, it delivers up to 33.2dBm of peak power with a maximum PAE of 60%. At the 1-dB compression point, the output power is 31.8dBm with a PAE of 54%. Based on this SOI LDMOS power stage, a monolithic two-stage linear PA has been designed and fabricated. After load-pull characterization, a maximum output power of 32.8dBm has been measured with a corresponding PAE of 51 %. When tested with a 10MHz bandwidth 16QAM uplink LTE signal, the PA provides an output power of 27dBm with less than 3% EVM and 557mA current consumption under 3.6V supply. The obtained results represent a new step towards high efficiency SOI CMOS Inteurated 4G cellular RF front-ends.