A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit

This paper presents a dual-power-supply SRAM that reduces active and standby power from room temperature (RT) to high temperature (HT) using a BL power calculator (BLPC) and a digitally controllable retention circuit (DCRC). A test-chip is fabricated in a 28nm CMOS technology with a 0.120μm
²
6T-SRAM cell. With these schemes, active and standby power consumptions at 25°C are reduced by 27% and 85%, respectively.