An all-digital PLL using random modulation for SSC generation in 65nm CMOS

This paper introduces a digital PLL which uses high-frequency random modulation (RM), as opposed to low-frequency periodic modulation, to generate a spread spectrum clock (SSC). The implementation is straightforward and reduces accumulated jitter substantially (by a factor of 8 in our implementation) with no penalty to EMI reduction or to period jitter. As a key advantage, the proposed design allows one to reduce the depth of FIFOs needed for high-data-rate peripherals or to remove it completely in case of low-data-rate interfaces.