A configurable blind adaptive low-complexity time-domain equalizer for ADSL systems by auto-correlation minimization

This paper discusses the design and the field programmable gate array (FPGA) implementation of a blind adaptive time-domain equalizer intellectual property (IP) core for asymmetric digital subscriber line (ADSL) systems. The design can be configured to implement the low-complexity adjacent lag auto-correlation minimization algorithm (LALAM) and adjacent lag auto-correlation minimization algorithm using moving average method (ALAM-MA) to shorten the channel. The IP core is implemented for the Xilinx Vertix II Pro XC2VP7-FF672-5 to be used in ADSL receivers. The implementation operates at a maximum frequency of 27 MHz and 38 MHz for ALAM-MA and LALAM algorithms, respectively. Simulation at all levels including the gate level simulation is performed and compared with the floating point simulation of the algorithms.