Software design of giga-bit WLAN on coarse grained reconfigurable array processors

In this paper, we present a software-defined radio (SDR) implementation of the 4×4 MIMO-OFDM baseband receivers on a coarse-grained reconfigurable array (CGRA) processor operating at 1 GHz clock for IEEE 802.11ac, which can support over 1Gbps data rate. However, software implementation of 802.11ac is very challenging because of the increasing computational complexity supporting giga-bit data transmission up to 6.9Gbps. For the software implementation, we focus on two major design issues: the software optimization for CGRA processors and the solution design for the preamble latency requirement. By measuring the computational cycles on the CGRA processor, we show the feasibility of SDR implementation for the 4×4 MIMO receiver of the 802.11ac. The BER is also evaluated to confirm the robustness of fixed point implementation.