A novel high-performance CMOS 1 bit full-adder cell

In this paper we propose a low complexity full adder design featuring higher computing speed, lower operating voltage, and lower energy consumption. it uses the low power designs of the XOR and AND gates pass transistors and transmission gates, simulation results comparing the conventional cell to the standard implementation show its superiority different circuit structures and input patterns are used for simulation. Energy saving up to 40% is achieved in addition. The performance is edge of the proposed. Design in both speed and energy consumption becomes even more significant as the world length of the adder increases. we explain how exclusive (XOR/AND) are used to realize a general full adder circuit based on pass transistor, the performance of the proposed full adder is evaluated by the comparison of the simulation result obtained from cadence. There is a higher cost in terms of the design effort for the proposed adder.