Digital-to-Time Synthesizers: Separating Delay Line Error Spurs and Quantization Error Spurs

This paper analyzes the spurs due to delay line (DL) buffer mismatch errors and phase quantization errors in a digital-to-time conversion (DTC) direct frequency synthesizer. Applying the time/frequency axis scaling property of the Discrete Fourier Transform (DFT) to a close approximation of the general case of both buffer error and quantization error spurs, it is shown that the spur spectra for all possible output frequencies can be divided into a very small number of classes. All the spectra within a class are scaled and systematically re-arranged versions of each other. For a DTC with a phase accumulator with I integer and M fractional bits, this result simplifies the number of spectra from 2
^(I+M)
to M. The condition that allows separation of the buffer errors spur locations from the quantization error spur location is derived. Spurs predicted based on the analysis match closely with actual measurements performed on a 90 nm CMOS DTC synthesizer. The spur analysis also applies to the flying adder (FA) synthesizer.