Standard cell level parasitics assessment in 20nm BPL and 14nm BFF

It is shown that the performance impact of middle-of-line (MOL) patterning process variations can be reduced by 30% by relaxing the standard cell gate pitch by 10% in both 20nm bulk planar (BPL) and 14nm bulk finFET (BFF). Tungsten can safely replace copper in local interconnect IM2, which allows the MOL critical dimensions (CD) to be reduced by 40% in 20nm BPL, resulting in 5% performance improvement. In 14nm BFF, 10% performance degradation can be traded in for 40% smaller IM1 contact area, allowing for a cell silicon footprint benefit of up to 20%.