Thermo-mechanical design and optimization of micro copper pillar bump for electrical interconnection in 2.5D IC integration

Micro copper pillar bumps (μCPBs) have been an important electrical interconnect method for fine pitch I/O applications such as 2.5D IC integration. The thermal stress induced by the coefficient of thermal expansion (CTE) mismatch between a Cu/low-k silicon die, micro copper pillar bump and through silicon via (TSV) based silicon interposer is a significant reliability issue for 2.5D IC integration. During the whole IC packaging process, the Cu/low-k silicon interconnected with silicon interposer through μCPBs will undergo three times of lead-free reflow process: a. the first level assembly between Cu/low-k silicon die and silicon interposer wafer, b. the second level component assembly between the silicon interposer and organic substrate, c. the third level assembly between the component and printed circuit board (PCB). In order to investigate the stress distribution in the fragile low-k layer of silicon die, parametric finite element analysis (FEA) was carried out respectively for each of the three reflow processes. In finite element models of this paper, the μCPBs were used to realize the first level interconnection between a 5.1mm×5.1mm Cu/low-k die with a 50μm bump pitch of total 10404 I/O and a silicon interposer, and underfilling was carried out after both the first reflow and the second reflow process. The influence of different parameters/factors on the stress distribution is simulated. Results show that relatively thinner die thickness, larger bump diameter, larger PI opening, thinner PI thickness and smaller Al pad diameter may contribute to the low stress in the low-k layer during the reflow processes.